IBM Shows Sub-1-nm Chips, Targeting Production in 5 Years

2026-06-25 · Source: Big Data & AI News - EE Times · Field: Technology & Digital — Artificial Intelligence & Machine Learning, Emerging Technologies & Innovation · Depth: Expert, medium

Summary

IBM announced the world's first sub-1-nm (0.7-nm) chip manufacturing technology, called "nanostack," with initial production anticipated from partners in five years. This innovation is projected to enable nearly 100 billion transistors on a chip, effectively doubling the density of IBM's 2021 2-nm nanosheet device. The "nanostack" architecture builds on existing nanosheet technology, which is currently entering production at 3-nm and 2-nm nodes by major chipmakers like TSMC, Samsung, and Intel. IBM is collaborating with Rapidus to initiate 2-nm production next year. The technology involves stacking two nanosheet transistors vertically, separated by 9 nm, and is expected to significantly scale logic and SRAM, offering a 40% improvement in SRAM scaling compared to 2-nm, crucial for addressing the "memory wall" in AI processors. IBM also partners with Lam Research on sub-1-nm node development.

Key takeaway

For AI Hardware Engineers and Architects planning future processor designs, IBM's sub-1-nm nanostack technology signals a significant shift in chip density and memory integration. You should anticipate a decade of scaling advancements, particularly in SRAM, which will alleviate the "memory wall" for data-heavy AI workloads. Consider how this vertical stacking approach could influence your design choices for ultra-dense 3D ICs and next-generation AI accelerators.

Key insights

IBM's "nanostack" technology enables sub-1-nm chips with unprecedented transistor density and SRAM scaling for future AI processors.

Principles

• Vertical stacking extends Moore's Law.
• Independent optimization enhances FETs.
• Addressing "memory wall" is critical for AI.

Method

IBM's nanostack uses sequential integration, stacking layers of nanosheet transistors vertically on a single chip via thin dielectric bonding, allowing independent optimization of top and bottom FETs.

In practice

• Design AI chips with increased SRAM.
• Explore 3D IC architectures for density.

Topics

• Sub-1-nm Chips
• Nanostack Technology
• 3D ICs
• SRAM Scaling
• AI Processors
• High-NA EUV Lithography
• Semiconductor Manufacturing

Best for: AI Hardware Engineer, AI Architect, Tech Journalist

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Editorial summary, takeaway, and curation by AIssential. Original article published by Big Data & AI News - EE Times.