IBM and Lam Research partner on sub-1nm logic scaling technologies

2026-03-11 · Source: Tech Monitor · Field: Technology & Digital — Semiconductor Technology & Manufacturing, Artificial Intelligence & Machine Learning, Emerging Technologies & Innovation · Depth: Expert, quick

Summary

IBM and Lam Research have established a five-year partnership focused on developing new materials and fabrication processes to achieve sub-1nm logic scaling. This collaboration will leverage IBM's research facilities at the NY Creates Albany NanoTech Complex and Lam Research's advanced process tools, including dry resist technology, etch platforms, and deposition systems. The initiative will concentrate on advancing High-NA EUV lithography processes and creating capabilities for increasingly complex device architectures. The goal is to extend logic scaling beyond current limitations by building and validating process flows for nanosheet and nanostack devices, alongside backside power delivery, to support future generations of logic devices. This agreement builds on previous successful collaborations between the two companies on 7nm, nanosheet, and EUV process technologies.

Key takeaway

For AI Hardware Engineers and Research Scientists focused on next-generation chip design, this partnership signals a clear direction towards sub-1nm logic. You should prioritize understanding High-NA EUV lithography and the implications of nanosheet/nanostack devices and backside power delivery for future transistor performance. Consider how these advancements will impact your design methodologies and material selections for lower power and higher performance AI-era transistors.

Key insights

IBM and Lam Research are collaborating to achieve sub-1nm logic scaling using advanced lithography and novel device architectures.

Principles

• Collaboration accelerates semiconductor innovation.
• 3D scaling requires integrated material and process rethinking.

Method

The partnership will build and validate process flows for nanosheet and nanostack devices, and backside power delivery, utilizing High-NA EUV lithography and dry resist technology.

In practice

• Focus on High-NA EUV lithography.
• Explore nanosheet and nanostack architectures.

Topics

• Sub-1nm Logic Scaling
• High-NA EUV Lithography
• Nanosheet Devices
• Backside Power Delivery
• Semiconductor Manufacturing

Best for: AI Scientist, AI Hardware Engineer, Research Scientist, AI Architect

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Editorial summary, takeaway, and curation by AIssential. Original article published by Tech Monitor.