IBM introduces the smallest computer chip in the world

2026-06-25 · Source: IBM Research · Field: Technology & Digital — Artificial Intelligence & Machine Learning, Emerging Technologies & Innovation · Depth: Intermediate, medium

Summary

IBM has unveiled the world's first sub-1 nanometer computer chip technology, featuring transistors just 0.7 nanometers (7 angstroms) wide. This breakthrough, achieved through a "nanostack" architecture, allows for roughly 100 billion transistors on a fingernail-sized chip. The new 7 angstrom chips are 70% more efficient or 50% more powerful than IBM's previous 2 nanometer node chips from 2021. Key innovations include thin dielectric wafer bonding for 3D transistor stacking, new channel materials for independent optimization of NFET and PFET channels, and a 40% increase in SRAM scaling. This technology could boost AI accelerator performance from 1,500 TOPS to an estimated 9,000 TOPS, potentially reducing large language model training times from three months to a couple of weeks.

Key takeaway

For AI Scientists and Directors of AI/ML planning future infrastructure, IBM's 7 angstrom chips signal a significant shift in compute capabilities. You should anticipate hardware that can reduce large language model training from months to weeks, potentially boosting your accelerator performance sixfold to 9,000 TOPS. This advancement necessitates re-evaluating your hardware roadmaps and investment strategies to capitalize on forthcoming efficiency and power gains.

Key insights

IBM's 7 angstrom "nanostack" architecture enables unprecedented transistor density and efficiency, accelerating AI and future computing.

Principles

• 3D stacking enhances transistor density.
• Independent channel optimization improves performance.
• SRAM scaling addresses AI memory bottlenecks.

Method

The "nanostack" architecture involves thin dielectric wafer bonding to create multilayered 3D transistors, optimizing NFET/PFET channels independently, and scaling SRAM by 40% for increased memory capacity.

In practice

• Drastically cut LLM training times.
• Power future autonomous machines.
• Extend battery life for monitoring devices.

Topics

• Sub-1nm Chips
• Nanostack Architecture
• AI Accelerators
• LLM Training
• Transistor Density
• SRAM Scaling

Best for: Research Scientist, AI Hardware Engineer, AI Scientist, Director of AI/ML

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Editorial summary, takeaway, and curation by AIssential. Original article published by IBM Research.