IBM has unveiled chip technology that could help extend Moore’s Law another decade

2026-06-25 · Source: MIT Technology Review · Field: Technology & Digital — Emerging Technologies & Innovation, Artificial Intelligence & Machine Learning, Cloud Computing & IT Infrastructure · Depth: Intermediate, medium

Summary

IBM has unveiled a prototype chip featuring approximately 100 billion transistors, achieving twice the density of its 2021 technology, on an area the size of a fingernail. This breakthrough, dubbed "nanostack" architecture, addresses the limitations of Moore's Law by vertically stacking transistors in two layers, a departure from traditional horizontal scaling. The company reports that chips built with this new approach can perform up to 50% more work in the same timeframe and are up to 70% more energy efficient compared to previous advanced designs. Experts like Dan Hutcheson of TechInsights suggest this innovation could extend the semiconductor roadmap by another 10 to 15 years. IBM anticipates this general transistor layout, which uses complementary field-effect transistors (CFETs) with staggered layers for simplified wiring, will be widely adopted in various chip types, including GPUs and CPUs, within a decade.

Key takeaway

For AI Architects and Hardware Engineers evaluating future compute infrastructure, IBM's nanostack technology signals a significant shift in chip design. You should anticipate a new generation of processors offering up to 50% more performance and 70% greater energy efficiency, potentially extending hardware roadmaps by 10-15 years. Begin exploring how these vertically stacked CFET architectures could impact your system designs and energy budgets, especially for data center deployments.

Key insights

IBM's nanostack architecture vertically stacks transistors, extending Moore's Law by enabling higher density and efficiency.

Principles

• Vertical stacking overcomes planar scaling limits.
• CFETs enable multi-layer transistor integration.
• Low-temperature fabrication is crucial for stacking.

Method

Engineers fabricate transistors on one silicon layer, then place another silicon layer on top, fabricating a second layer of transistors directly above, and finally creating electrical connections.

In practice

• Deploy nanostack in GPUs and CPUs.
• Improve data center energy efficiency.
• Explore multi-tier chip manufacturing.

Topics

• Nanostack Architecture
• Moore's Law Extension
• Complementary FET
• Semiconductor Manufacturing
• Transistor Density
• Energy Efficiency

Best for: AI Hardware Engineer, Research Scientist, AI Architect

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Editorial summary, takeaway, and curation by AIssential. Original article published by MIT Technology Review.