What is IBM's nanostack chip architecture?

2026-06-25 · Source: IBM Research · Field: Technology & Digital — Artificial Intelligence & Machine Learning, Emerging Technologies & Innovation, Semiconductor Manufacturing & Hardware · Depth: Intermediate, medium

Summary

IBM has introduced nanostack, a new chip architecture enabling three-dimensional transistor construction, which represents a significant shift from 60-plus years of 2D scaling. This innovation allows for nearly two times greater transistor density per unit area compared to IBM's 2 nm node nanosheet technology, achieving nearly 100 billion transistors on a fingernail-sized chip. Initial projections indicate 70% less energy consumption and a 50% speedup over 2nm node chips. Nanostack fundamentally involves stacking nanosheets, with a key advancement being the sequential stacking of n-type and p-type transistors, allowing for independent material optimization and separate power/signal routing. This architecture, supported by technologies like High Numerical Aperture Extreme Ultraviolet (High NA EUV) lithography, is expected to extend logic technology scaling to 2040, offering 40% greater on-chip memory and dual backside power delivery.

Key takeaway

For AI Hardware Engineers and AI Architects designing next-generation chips, IBM's nanostack architecture signals a critical shift to 3D scaling. You should evaluate this technology's potential for achieving significantly higher transistor densities and performance, considering its projected 70% energy reduction and 50% speedup over 2nm nodes. Begin exploring how 3D design principles and advanced lithography like High NA EUV will impact your future chip development roadmaps.

Key insights

IBM's nanostack architecture enables 3D transistor stacking, significantly boosting density and performance beyond 2D scaling limits.

Principles

• 3D stacking overcomes 2D scaling limits.
• Separate n-type/p-type allows material optimization.
• Backside power delivery improves density.

Method

Nanostack fabrication involves stacking silicon wafers with alternating transistor arrangements, utilizing wafer-level bonding and High NA EUV lithography for precise patterning.

In practice

• Faster AI model training and inference.
• Longer laptop and mobile phone battery life.
• Reduced power consumption for devices.

Topics

• Nanostack Architecture
• 3D Logic Scaling
• High NA EUV Lithography
• Transistor Density
• Semiconductor Manufacturing
• AI Hardware

Best for: AI Hardware Engineer, AI Architect, Director of AI/ML

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Editorial summary, takeaway, and curation by AIssential. Original article published by IBM Research.