TSMC Defends Transistor Scaling Amid Huawei’s ‘Her’s Law’ Proposal

2026-06-01 · Source: Big Data & AI News - EE Times · Field: Technology & Digital — Emerging Technologies & Innovation, Artificial Intelligence & Machine Learning · Depth: Expert, short

Summary

At TSMC's European Symposium on 06.01.2026, Senior VP Kevin Zhang addressed Huawei's "Her's Law" proposal, which advocates measuring semiconductor progress by overall speedup (Tao scaling) rather than transistor density, a method Huawei adopted due to its lack of EUV access beyond 7-nm nodes. Zhang affirmed the transistor's continued criticality, noting it consumes the most R&D effort and provides significant energy efficiency gains, such as 30% from N2 to A14 process nodes, far exceeding low-single-digit improvements from data center power system upgrades. While acknowledging 3D integration as a long-standing concept, Zhang redefined "density" to include the vertical dimension, recognizing die stacking as an innovative approach to increase computation per cubic centimeter. TSMC is also exploring future 3D-stacked technologies like CFETs, which place p-type and n-type FETs on top of each other within the same die. Despite these advancements, TSMC acknowledges a slowdown in transistor density scaling after 3nm.

Key takeaway

For AI Hardware Engineers and Architects designing next-generation systems, recognize that traditional transistor scaling remains paramount for achieving significant energy efficiency, offering 30% gains from N2 to A14 nodes. While density scaling has slowed, embrace 3D integration and die stacking, like CFETs, as crucial strategies to boost computation per cubic centimeter in data centers. Your roadmap should balance advanced node development with innovative vertical integration to maximize performance and efficiency.

Key insights

TSMC asserts transistor scaling and 3D integration are vital for semiconductor advancement, despite Huawei's alternative metrics.

Principles

• Transistor-level computation is fundamental.
• Density now includes the vertical dimension.
• Scaling yields significant energy efficiency.

Method

Huawei's Tao scaling measures overall speedup via 3D integration. TSMC's CFETs stack p-type and n-type FETs within the same die.

In practice

• Evaluate 3D integration for density.
• Investigate CFETs for future designs.
• Prioritize transistor scaling for efficiency.

Topics

• TSMC
• Huawei
• Transistor Scaling
• 3D Integration
• CFETs
• Semiconductor Manufacturing

Best for: AI Hardware Engineer, AI Architect, Tech Journalist

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Editorial summary, takeaway, and curation by AIssential. Original article published by Big Data & AI News - EE Times.