🗞️ China’s Huawei reveals a new chip design breakthrough which can close its gap with TSMC and Intel

2025-08-21 · Source: Rohan's Bytes · Field: Technology & Digital — Artificial Intelligence & Machine Learning, Emerging Technologies & Innovation, Software Development & Engineering · Depth: Intermediate, long

Summary

Huawei has unveiled a new chip design methodology, "τ Scaling" (Tau Scaling), aimed at achieving advanced performance without solely relying on shrinking transistor sizes. This breakthrough, detailed in a paper introducing "LogicFolding," proposes measuring chip progress by reducing signal delay (τ) across wires, memory paths, and software layers, rather than just transistor geometry. LogicFolding specifically optimizes circuit layouts by placing logic blocks closer to shorten critical wires and reduce electrical drag. Huawei claims this approach, also known as Her's Law, has already been used in mass-producing 381 chips. The company projects future high-end chips could reach 1.4nm-class (14Å) density by 2031, aligning with TSMC and Intel's 2029 targets, despite US sanctions blocking Huawei's access to TSMC since 2020. The next Kirin phone chip will be the first full test of Tau Scaling Law.

Key takeaway

For chip architects and hardware engineers facing manufacturing constraints, Huawei's "τ Scaling" presents a critical alternative to traditional process node advancements. You should investigate optimizing for signal delay (τ) and applying "LogicFolding" principles to your designs, especially if access to leading-edge lithography is limited. This strategy suggests that significant performance gains can still be achieved by focusing on full-stack timing and circuit layout, potentially enabling competitive density targets like 1.4nm-class without relying solely on smaller transistors.

Key insights

Chip progress can shift from transistor shrinkage to optimizing signal delay (τ) across the entire system stack.

Principles

• Reduce signal delay (τ) across the full stack.
• LogicFolding shortens critical wires for performance.
• Achieve density without advanced lithography.

Method

Implement "LogicFolding" to fold logic blocks closer, shortening wires and reducing resistance/capacitance. Apply "τ Scaling" across transistors, circuits, architecture, software, and interconnects.

In practice

• Evaluate chip designs for signal delay (τ) reduction.
• Optimize circuit layouts for shorter wire paths.
• Explore full-stack timing optimizations.

Topics

• Chip Design
• Semiconductor Manufacturing
• Huawei
• Tau Scaling
• LogicFolding
• Kirin Chips
• US Sanctions

Best for: AI Scientist, AI Engineer, Director of AI/ML

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• Huawei Unveils Tau Scaling Law for Next-Gen Chip Evolution — Huawei's Tau Scaling Law and LogicFolding enable 3D chip architectures to reduce signal transmission times, overcoming Moore's Law limits.
• Necessity is the Mother of Invention: Huawei Replaces Moore’s Law With Her’s Law — Sanctions drive innovation, compelling Huawei to accelerate 3D stacking for performance gains beyond traditional geometric scaling.
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Editorial summary, takeaway, and curation by AIssential. Original article published by Rohan's Bytes.