Records Fall for 3D Chip Tech

2026-06-25 · Source: IEEE Spectrum · Field: Technology & Digital — Emerging Technologies & Innovation, Artificial Intelligence & Machine Learning · Depth: Advanced, quick

Summary

New records have been set in 3D chipmaking using hybrid bonding technology, crucial for meeting growing computing demands in AI and high-performance computing. At the IEEE Electronic Components and Technology Conference (ECTC), Imec achieved a wafer-to-wafer (W2W) bond pitch of 200 nanometers, down from 250 nm, by improving chemical mechanical polishing and wafer alignment. Concurrently, CEA-Leti demonstrated a die-to-wafer (D2W) pitch of 1 micrometer, a 50% reduction from 2 μm, enabling a million connections per square millimeter. These advancements significantly increase interconnect density and reduce power consumption. The article also highlights Huawei's implementation of a 1.5 μm hybrid-bonding pitch in its Kirin processors to enhance transistor density amidst export controls, underscoring the technology's strategic importance. While research pushes boundaries, mass production still faces challenges in speed and replicability, with D2W potentially gaining preference for its flexibility.

Key takeaway

For AI Hardware Engineers designing next-generation semiconductor devices, these hybrid bonding advancements mean you can achieve significantly higher interconnect densities and lower power consumption. Focus on integrating die-to-wafer (D2W) hybrid bonding, as its flexibility for mixing chip functionalities is becoming the preferred industry direction. Prioritize improving alignment accuracy and chemical mechanical polishing processes to push beyond current mass production pitches of 6-9 µm.

Key insights

Hybrid bonding advances significantly increase 3D chip interconnect density, crucial for next-gen AI and HPC devices.

Principles

• Finer bond pitches lower power and densify interconnects.
• Die-to-wafer offers greater flexibility than wafer-to-wafer.
• Electrical testing and reliability data validate pitch records.

Method

Hybrid bonding involves precisely aligning and joining copper and insulation pads on chip faces, then applying heat to create electrical connections.

In practice

• Implement D2W hybrid bonding for flexible chip stacking.
• Improve CMP and alignment for denser interconnects.
• Evaluate electrical yield for 1 μm D2W pitches.

Topics

• 3D Chip Stacking
• Hybrid Bonding
• Wafer-to-Wafer Bonding
• Die-to-Wafer Bonding
• Semiconductor Manufacturing
• High-Performance Computing
• AI Hardware

Best for: AI Hardware Engineer, Research Scientist, Director of AI/ML

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Editorial summary, takeaway, and curation by AIssential. Original article published by IEEE Spectrum.