Necessity is the Mother of Invention: Huawei Replaces Moore’s Law With Her’s Law

2026-05-27 · Source: Big Data & AI News - EE Times · Field: Technology & Digital — Emerging Technologies & Innovation, Semiconductor Manufacturing & Design, Artificial Intelligence & Machine Learning · Depth: Intermediate, medium

Summary

Huawei president He Tingbo unveiled "Her's Law" (also "He's Law") at IEEE ISCAS 2026 in Shanghai on May 26, presenting China's strategy to circumvent U.S. sanctions on EUV technology for chip manufacturing. This initiative aims to achieve performance equivalent to the industry's 14Å node by 2031, positioning Huawei approximately three years behind Intel's 2027 and TSMC's 2028 targets. The core of Her's Law is an accelerated 3D stacking roadmap, termed LogicFolding, which reduces parasitic RC by vertically stacking dies with an aggressive 2 µm hybrid bonding pitch. Huawei claims LogicFolding increased SoC P-core power efficiency by 41% and maximum clock frequency by 12.7% on a Kirin 2026 design compared to its 2D counterpart. He also introduced τ scaling, reframing progress beyond transistor density to encompass any system performance improvement. While the industry is developing 3D stacking, Huawei has significantly accelerated its commercialization.

Key takeaway

For AI Hardware Engineers and Architects evaluating future chip roadmaps, Huawei's accelerated 3D stacking via LogicFolding presents a significant alternative to EUV-dependent geometric scaling. You should consider integrating advanced hybrid bonding techniques, like those achieving 2 µm pitch, into your design strategies to mitigate supply chain risks or achieve performance gains where traditional node shrinkage is constrained. This approach demonstrates that substantial performance improvements are achievable through system-level innovation, even when facing manufacturing limitations.

Key insights

Sanctions drive innovation, compelling Huawei to accelerate 3D stacking for performance gains beyond traditional geometric scaling.

Principles

• Progress can be redefined beyond transistor density.
• Aggressive 3D stacking reduces critical path wire length.
• Early commercialization of advanced tech offers competitive advantage.

Method

Huawei's LogicFolding uses vertical die stacking and 2 µm hybrid bonding pitch to reduce parasitic RC and improve SoC performance.

In practice

• Explore 3D stacking with 2 µm hybrid bond pitch for performance.
• Redefine performance metrics beyond traditional node scaling.

Topics

• 3D Stacking
• Hybrid Bonding
• Semiconductor Manufacturing
• Chip Design
• Huawei
• EUV Sanctions
• τ Scaling

Best for: AI Hardware Engineer, AI Architect, Director of AI/ML

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Editorial summary, takeaway, and curation by AIssential. Original article published by Big Data & AI News - EE Times.