This chip startup just raised $135M on a bet that AI’s biggest bottleneck isn’t compute — it’s memory

2026-05-29 · Source: AI News & Artificial Intelligence | TechCrunch · Field: Technology & Digital — Artificial Intelligence & Machine Learning, Cloud Computing & IT Infrastructure, Emerging Technologies & Innovation · Depth: Intermediate, short

Summary

XCENA, a four-year-old startup with offices in South Korea and the U.S., recently secured \$135 million in Series B funding at a \$570 million valuation, bringing its total raised to \$185 million. The company is addressing a critical AI bottleneck: memory inefficiency, rather than compute. Its proprietary MX1 chip integrates compute capabilities directly within DRAM modules, utilizing CXL to process data near memory and eliminate costly round trips between CPUs, GPUs, and memory. This architecture aims to significantly reduce AI infrastructure costs, potentially allowing tasks that once required 10 servers to run on just one. The MX1, currently a prototype, is slated for mass production by Samsung's foundry lines by late 2026, with revenue projected for 2027. XCENA differentiates from rivals like Astera Labs and Marvell through its thousands of RISC-V based, data-optimized cores and extensive vertical integration in chip design.

Key takeaway

For AI Architects and Hyperscaler infrastructure leads optimizing large-scale inference, recognize that memory architecture is a critical bottleneck, not just compute. Your current CPU/GPU-memory data round trips are inefficient and costly. You should evaluate emerging memory-centric solutions like XCENA's MX1, which promise significant server consolidation and cost savings by processing data closer to DRAM. Consider how integrating CXL-based, compute-in-memory approaches could reshape your infrastructure strategy and reduce operational expenses.

Key insights

AI inference is increasingly a memory scaling problem, not solely a compute challenge.

Principles

• Compute-in-memory reduces expensive data round trips.
• Memory-centric architectures are gaining market traction.
• Vertical integration enhances chip performance and differentiation.

Method

The MX1 chip uses CXL to connect to the CPU, processing data directly within the memory module to handle tasks like preprocessing and KV cache management before data leaves memory.

In practice

• Evaluate memory-centric solutions for AI infrastructure.
• Investigate CXL for improved memory-processor communication.
• Consider RISC-V for custom, efficient data processing cores.

Topics

• AI Inference
• Memory-centric Architecture
• Compute Express Link
• XCENA MX1 Chip
• DRAM
• RISC-V
• AI Infrastructure Costs

Best for: CTO, VP of Engineering/Data, Director of AI/ML, AI Hardware Engineer, AI Architect, Investor

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Editorial summary, takeaway, and curation by AIssential. Original article published by AI News & Artificial Intelligence | TechCrunch.