AMD Snaps MEXT to Break the Memory Wall

· Source: Big Data & AI News - EE Times · Field: Technology & Digital — Artificial Intelligence & Machine Learning, Cloud Computing & IT Infrastructure · Depth: Intermediate, medium

Summary

AMD has acquired MEXT, a specialist in predictive memory technology, to address the "memory wall" bottleneck in AI and data center deployments. This acquisition highlights that AI scaling is increasingly a memory problem, not just a compute problem, with DRAM becoming the scarcest and most expensive server component, accounting for nearly 60% of server costs in 2026, up from 50%. MEXT's technology creates a hybrid memory architecture that combines DRAM with flash storage. It uses an AI engine to identify "cold" memory pages, offload them to flash (which is 50x cheaper and 30x lower power), and then proactively move them back to DRAM before needed, maintaining performance. This approach aims to deliver DRAM-class performance with flash-level economics, reducing infrastructure costs and expanding usable memory capacity. For AMD, this strengthens its CPU and GPU offerings, particularly for its MI300 and MI355X accelerators, and enhances its ROCm software ecosystem against Nvidia's CUDA.

Key takeaway

For AI Architects or Directors of AI/ML evaluating data center infrastructure, AMD's acquisition of MEXT signals a critical shift towards software-driven memory optimization. You should prioritize solutions that address memory bottlenecks, as DRAM costs and underutilization significantly impact TCO and scaling. Consider how predictive memory technologies could reduce your server memory spend, improve hardware utilization, and enhance performance for large AI workloads, especially with HBM-reliant accelerators.

Key insights

AI scaling's memory wall can be broken by AI-driven predictive memory tiering, combining DRAM performance with flash economics.

Principles

Method

MEXT's method identifies cold memory pages, offloads them to flash, then uses an AI engine to predict future needs, proactively pushing pages back to DRAM to maintain performance.

Topics

Best for: MLOps Engineer, Investor, CTO, AI Architect, Director of AI/ML, AI Hardware Engineer

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Editorial summary, takeaway, and curation by AIssential. Original article published by Big Data & AI News - EE Times.