Startup Wants to Speed Up Chip Design With AI in RTL to GDSII Path

2026-02-26 · Source: Big Data & AI News - EE Times · Field: Technology & Digital — Artificial Intelligence & Machine Learning, Semiconductor Design · Depth: Intermediate, medium

Summary

Tattvam AI, a London-based startup, has emerged from stealth with $1.7 million in early investment to apply AI to the physical design stage of chip development, aiming to reduce design cycles from years to weeks. The company's co-founder, Bragadeesh S., highlights that current physical design processes, which convert system RTL to GDSII, involve months-long iterative tasks like timing closure and clock tree synthesis, leading to two-to-three-year design cycles for complex chips. Tattvam AI is developing a local AI system, an "intelligence layer," that understands circuit design from first principles to autonomously suggest actions and insights within hours. This system is designed to integrate with existing EDA tools, not replace them, and will initially focus on timing closure challenges, with plans to expand to other physical design aspects.

Key takeaway

For design services companies and hyperscalers developing custom chips, Tattvam AI's approach offers a path to significantly compress physical design timelines. You should evaluate how this "intelligence layer" can integrate with your current EDA tools to automate iterative tasks like timing closure, potentially reducing design cycles from years to weeks and mitigating the risk of costly respin delays.

Key insights

AI can dramatically accelerate chip physical design by understanding circuits from first principles and automating complex reasoning tasks.

Principles

• Chip design is a reasoning problem over a vast search space.
• Understanding circuit structure from first principles is key for AI in design.

Method

Tattvam AI trains domain-specific models using synthetic datasets inspired by ARC-AGI benchmarks and mathematical theorems to replicate real chip tape-out processes and generate high-quality training data.

In practice

• Integrate AI as an intelligence layer within existing EDA workflows.
• Focus initial AI application on specific, time-consuming design "wedges."

Topics

• Chip Design AI
• Physical Design Automation
• AI Reasoning Models
• Semiconductor Design
• Timing Closure

Best for: Investor, AI Engineer, Machine Learning Engineer, AI Architect

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Editorial summary, takeaway, and curation by AIssential. Original article published by Big Data & AI News - EE Times.