AUTOGATE: Automated Clock Gating via Toggling-Aware LLM-based RTL Rewriting
Summary
AUTOGATE is the first agentic framework designed for industry-grade Register-Transfer Level (RTL) power optimization, specifically targeting fine-grain clock gating (FGCG). It addresses the limitations of current manual FGCG optimization and prior LLM-based approaches, which struggle with long waveform traces and scaling to large hierarchical codebases while maintaining correctness. AUTOGATE employs an ML-LLM co-design, utilizing an ML-based clustering algorithm to distill raw toggling traces into compact representations that guide LLM-based RTL rewriting, avoiding direct LLM processing of raw waveform data. For scalability, it uses a hierarchical multi-agent architecture to decompose designs into optimizable modules. Evaluations show AUTOGATE reduces dynamic power by 49.31% on average for small designs, 19.34% on NVDLA, 7.96% on BlackParrot, and up to 6.86% on highly optimized proprietary production designs.
Key takeaway
For AI Hardware Engineers optimizing power in complex RTL designs, AUTOGATE offers a significant advancement over manual or prior LLM-based methods. You should consider integrating this ML-LLM co-design approach to overcome challenges with long waveform traces and hierarchical scalability. This framework demonstrates substantial dynamic power reductions, making it a viable solution for improving energy efficiency in your next-generation silicon.
Key insights
AUTOGATE automates fine-grain clock gating for RTL power reduction using an ML-LLM co-design and hierarchical multi-agent architecture.
Principles
- Distill complex data for LLM guidance.
- Decompose large designs hierarchically.
- Combine ML and LLMs for specialized tasks.
Method
AUTOGATE uses ML clustering to condense toggling traces, guiding LLM-based RTL rewriting. A hierarchical multi-agent system then decomposes and coordinates optimization across design hierarchies.
In practice
- Apply ML clustering to waveform data.
- Implement multi-agent design decomposition.
- Integrate LLMs for RTL rewriting tasks.
Topics
- Fine-Grain Clock Gating
- RTL Power Optimization
- LLM-based Design
- Multi-Agent Systems
- Hardware Architecture
- Machine Learning Clustering
Best for: Research Scientist, AI Scientist, AI Hardware Engineer, Machine Learning Engineer
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Editorial summary, takeaway, and curation by AIssential. Original article published by Artificial Intelligence.