Beyond Chiplets, CMOS 2.0 Moves Scaling into the Circuit

2026-06-17 · Source: Big Data & AI News - EE Times · Field: Technology & Digital — Emerging Technologies & Innovation, Artificial Intelligence & Machine Learning, Robotics & Autonomous Systems · Depth: Expert, medium

Summary

Imec's "CMOS 2.0" introduces a new semiconductor scaling paradigm that extends beyond traditional chiplets and advanced packaging by disaggregating circuits at a fundamental level. This roadmap aims to re-architect systems from the ground up, potentially splitting N-type and P-type devices across two layers to create new ways to connect logic, memory, I/O, and power delivery within a 3D architecture. Driven by the "memory wall" in AI workloads, which demands massive data movement, CMOS 2.0 seeks to increase the density of vertical connections significantly, reducing energy consumption and boosting bandwidth. This approach requires a system-centric view of silicon design, integrating CPUs, accelerators, memory, and software. While currently a roadmap, imec anticipates design infrastructure in five years and initial implementations within ten years, addressing the limitations of current scaling methods.

Key takeaway

For AI Architects designing next-generation systems, recognize that traditional chiplet integration will soon be insufficient. You must anticipate a shift towards circuit-level disaggregation and ultra-dense vertical integration, as proposed by imec's CMOS 2.0. This paradigm will redefine how you approach memory, logic, and power delivery, demanding a system-centric design view. Start exploring tools and methodologies for multi-tier architectures and high-density bonding now to prepare for implementations expected within ten years.

Key insights

CMOS 2.0 disaggregates circuits at the lowest level for ultra-dense 3D integration, driven by AI's data movement demands.

Principles

• Scaling must move beyond packaging into circuit repartitioning.
• System efficiency defines AI workload sustainability per watt.
• Vertical integration is crucial for efficient power and data delivery.

Method

CMOS 2.0 proposes re-architecting circuits from the ground up, potentially completing N-type and P-type devices across two layers to enable extremely dense vertical connections for logic, memory, I/O, and power.

In practice

• Separate low-power and high-performance logic across tiers.
• Design for tens of millions of vertical connections/mm².
• Integrate CPUs, accelerators, memory, I/O as one 3D system.

Topics

• CMOS 2.0
• 3D System Integration
• Circuit Repartitioning
• AI Workloads
• Memory-Compute Bottleneck
• Wafer-to-Wafer Bonding

Best for: AI Hardware Engineer, AI Architect, CTO

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Editorial summary, takeaway, and curation by AIssential. Original article published by Big Data & AI News - EE Times.