Scaling the Next Generation of Multi-Die Systems

2026-05-21 · Source: Big Data & AI News - EE Times · Field: Technology & Digital — Artificial Intelligence & Machine Learning, Emerging Technologies & Innovation, Semiconductor Design & Hardware · Depth: Advanced, short

Summary

The "EE Times Presents: The Road To Chiplet Scalability" virtual event, scheduled for June 23 and 24, will address the critical challenges of scaling multi-die chiplet systems in production. The conference shifts focus from the viability of chiplets to practical implementation, tackling issues like interconnect, packaging, power, thermals, and design complexity. Day one, "Accelerating the Design Flow," will explore how chiplet architectures impact semiconductor design methodologies and EDA tools, featuring keynotes from Cognichip's Stelios Diamantidis on AI in EDA and AMD's Garrett Wyatt on current EDA bottlenecks. Day two, "Scaling Chiplet Technologies," will delve into advanced packaging, 2D/3D integration, manufacturing, and interconnects, with Marvell's Preet Virk discussing XPU-to-XPU bandwidth for AI infrastructure. The event aims to bridge the gap between chiplets' potential and their real-world scaling limitations, including yield, interoperability, and thermal density.

Key takeaway

For AI Architects evaluating multi-die system designs, recognize that current EDA toolflows and interconnect limitations are significant bottlenecks. Your focus should shift to early physical design considerations and exploring advanced packaging and 2D/3D integration to achieve scalable AI infrastructure. Actively investigate solutions for XPU-to-XPU bandwidth and consider how AI-driven EDA tools could streamline your development process, mitigating risks associated with yield and interoperability in complex chiplet systems.

Key insights

The semiconductor industry is focused on overcoming practical scaling challenges for chiplet architectures in production, moving beyond initial adoption questions.

Principles

• Physical design considerations must shift earlier.
• EDA toolflows are a bottleneck for multi-chiplet designs.
• XPU-to-XPU bandwidth is a critical scaling need.

In practice

• Consider AI integration into EDA toolflows.
• Evaluate advanced packaging for 2D/3D integration.
• Address interconnect proliferation for AI infrastructure.

Topics

• Chiplets
• Multi-die Systems
• EDA Tools
• Advanced Packaging
• AI Infrastructure
• Interconnect Technology

Best for: AI Hardware Engineer, AI Architect, Director of AI/ML

Related on AIssential

• CEA-Leti CEO: AI’s Real Bottleneck Is Architecture — AI's future hinges on architectural innovation, integrating memory, compute, and communication efficiently, alongside addressing critical energy constraints.
• Chiplets, Ecosystems, and Europe’s Post-Fab Semiconductor Strategy — Europe shifts its semiconductor strategy from fab-centric to chiplet-driven ecosystem leadership, responding to AI's demands.
• [Server] The Bottleneck of Compute: How Humanity Weaves the Soul of Memory with Silicon — HBM overcomes the "Memory Wall" by prioritizing wide parallel data paths and 3D stacking over frequency.
• What They Just Built Is Unreal — Imec drives future computing by inventing post-Moore's Law chip architectures and materials, enabling continued technological advancement.
• Accelerating Chipmaking Innovation for the Energy-Efficient AI Era — The AI era demands a coupled, accelerated co-innovation model for energy-efficient semiconductor design, replacing slow, siloed R&D.
• Coherent Breaks Ground on Expanded Texas Facility, Scaling AI’s Optical Backbone — Optical interconnects, leveraging 6-inch indium phosphide wafers, are fundamental for scaling high-performance AI infrastructure efficiently.

Open in AIssential →

Editorial summary, takeaway, and curation by AIssential. Original article published by Big Data & AI News - EE Times.