Europe's €830M Last Stand For Chip Sovereignty May Depend On Grenoble

2026-02-24 · Source: The French Tech Journal · Field: Technology & Digital — Artificial Intelligence & Machine Learning, Emerging Technologies & Innovation, Internet of Things (IoT) & Connected Devices · Depth: Intermediate, medium

Summary

Europe is investing €830 million into the FAMES (FD-SOI Pilot Line for Applications with embedded non-volatile Memories, RF, 3D Integration & PMIC, to ensure European Sovereignty) pilot line in Grenoble, France, to regain semiconductor manufacturing independence. This initiative, co-funded by the European Commission under the Chips Act, aims to boost Europe's share of global chip production, which has fallen from 30% to 5-7%. The FAMES line, coordinated by CEA-Leti, features a new 2,000-square-meter cleanroom with 300mm tools, including space for ASML EUV lithography. It focuses on advancing FD-SOI technology to 10nm and 7nm nodes for edge AI applications, integrating digital, analog, and RF functions. The project, involving 11 partners across eight countries and supported by 44 industry stakeholders like STMicroelectronics and GlobalFoundries, also emphasizes a "lab-to-market" methodology to accelerate technology transfer and product development.

Key takeaway

For CTOs and R&D leaders evaluating semiconductor supply chain resilience, the FAMES pilot line signifies Europe's commitment to re-establishing domestic advanced chip manufacturing. You should consider engaging with this open-access facility to prototype and de-risk new FD-SOI based technologies, particularly for edge AI applications, to reduce reliance on external foundries and accelerate your product development cycles within Europe.

Key insights

Europe's FAMES pilot line aims to restore semiconductor sovereignty by accelerating advanced chip development for edge AI.

Principles

• Semiconductor independence is critical for economic sovereignty.
• Public-private collaboration accelerates industrial capability.
• Rapid technology transfer is essential for market competitiveness.

Method

The "lab-to-market" methodology involves two phases: generic technology transfer from lab to industry, followed by on-site engineering support at the partner's premises to develop first products.

In practice

• Utilize FD-SOI for low-power, high-performance edge AI.
• Explore 10nm and 7nm FD-SOI for advanced applications.
• Integrate non-volatile memories, RF, and 3D components.

Topics

• Semiconductor Manufacturing
• FD-SOI Technology
• Edge AI
• European Chips Act
• Technological Sovereignty

Best for: CTO, Executive, Investor, Policy Maker, Director of AI/ML, Research Scientist

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Editorial summary, takeaway, and curation by AIssential. Original article published by The French Tech Journal.