EU DARE Project Is Scrambling to Replace Codasip

2026-04-17 · Source: Big Data & AI News - EE Times · Field: Technology & Digital — Artificial Intelligence & Machine Learning, Cloud Computing & IT Infrastructure, Cybersecurity & Data Privacy · Depth: Intermediate, medium

Summary

The European High-Performance Computing Joint Undertaking (EuroHPC JU) and the Digital Autonomy with RISC-V in Europe (DARE) consortium, backed by a €240 million budget, are addressing the implications of a strategic pivot by partner Codasip. Codasip, a Munich-based company, recently announced a divestment of its low-end RISC-V processor design business to an undisclosed U.S. public semiconductor company and a shift towards cyber-resilient architectures utilizing CHERI technology. This realignment introduces uncertainty for the DARE project, which aims to develop processors and accelerators for European data centers, particularly regarding its general-purpose processor (GPP) chiplet and associated architectural and financial planning. Stakeholders, including the Barcelona Supercomputing Center (BSC) and OpenChip, are exploring alternatives and emphasizing the need for robust European semiconductor companies and more agile investment processes.

Key takeaway

For AI Architects and Policy Makers focused on European digital autonomy, Codasip's divestment underscores the critical need for diversified supply chains and robust regional investment. You should advocate for faster, more agile funding mechanisms and support the development of multiple European partners to ensure long-term independence in high-performance computing and RISC-V intellectual property.

Key insights

Codasip's strategic pivot impacts the DARE project, highlighting challenges in European semiconductor independence and investment.

Principles

• Cyber-resilience requires architectural integration, not just software patches.
• European semiconductor sovereignty needs strong regional companies.
• Investment culture significantly impacts startup viability.

Method

Codasip is expanding its secure processor portfolio using Capability Hardware Enhanced RISC Instructions (CHERI) technology to build cyber-resilience from the architecture outward, including FPGAs and custom silicon.

In practice

• Integrate security into system architecture from initial design.
• Focus on business acumen alongside technical merit for viability.
• Seek mechanisms to match private and public funds for startups.

Topics

• EU DARE Project
• Codasip Strategic Pivot
• RISC-V Processors
• European High-Performance Computing
• Cyber-Resilient Architectures

Best for: CTO, AI Hardware Engineer, AI Architect, Policy Maker

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Editorial summary, takeaway, and curation by AIssential. Original article published by Big Data & AI News - EE Times.