ExaGEMM: Exploration Framework for CPU-Driven ML Inference via Associative In-Register Computing for Low-Bit GEMM

2026-07-16 · Source: Machine Learning · Field: Technology & Digital — Artificial Intelligence & Machine Learning, AI Hardware & Architecture · Depth: Expert, quick

Summary

ExaGEMM is a novel workload-aware codesign and exploration framework designed for CPU-native low-bit General Matrix Multiply (GEMM) operations, crucial for efficient ML inference. It leverages register-resident Look-Up Table (LUT) execution, building on the insight that existing SIMD datapaths can handle table generation and accumulation, requiring only a new in-register select/feed mechanism with explicitly modeled cost. ExaGEMM analytically co-explores parameterized kernels and lightweight SIMD ISA support, effectively pruning the candidate space by 99.2% before simulation. This framework identifies non-dominated support points and generates necessary ISA specifications, gem5 patches, and GEMM kernels for validation. Across representative ML models and CPU targets, ExaGEMM demonstrates a 13.29x latency improvement over software-only baselines, highlighting the critical role of workload-aware frontier selection for mixed-precision LLM workloads.

Key takeaway

For AI Hardware Engineers and ML Architects optimizing CPU-driven ML inference, ExaGEMM's approach offers a significant pathway to efficiency. You should investigate integrating in-register associative computing and workload-aware codesign principles to overcome the limitations of conventional CPUs for low-bit GEMM. This method can yield substantial latency improvements, up to 13.29x, particularly for mixed-precision LLM workloads, by intelligently leveraging existing SIMD capabilities and minimal new hardware.

Key insights

ExaGEMM enables efficient low-bit GEMM on CPUs via in-register associative computing and workload-aware codesign.

Principles

• Very-low-bit execution is inefficient on conventional CPUs.
• Existing SIMD datapaths can be repurposed for LUT generation and accumulation.
• Workload-aware frontier selection is critical for mixed-precision LLM performance.

Method

ExaGEMM analytically co-explores parameterized kernels and lightweight SIMD ISA support, prunes candidates by 99.2%, identifies non-dominated support points, and generates ISA specs, gem5 patches, and GEMM kernels.

In practice

• Optimizing CPU-driven ML inference.
• Implementing low-bit GEMM operations.
• Improving mixed-precision LLM performance.

Topics

• Low-bit GEMM
• CPU Inference
• Hardware Architecture
• SIMD ISA
• LLM Optimization
• ML Inference

Best for: AI Engineer, NLP Engineer, AI Scientist, AI Hardware Engineer, Machine Learning Engineer, AI Architect

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Editorial summary, takeaway, and curation by AIssential. Original article published by Machine Learning.