Largest Probabilistic Computer Hits 1 Million P-Bits

2026-07-18 · Source: IEEE Spectrum · Field: Technology & Digital — Emerging Technologies & Innovation, Artificial Intelligence & Machine Learning · Depth: Expert, short

Summary

Scientists have developed the largest probabilistic computer to date, featuring 1 million "probabilistic bits" (p-bits) spread across multiple chips. Detailed in a June 24 ArXiv preprint by Kerem Çamsarı's team, this machine utilizes 18 networked field-programmable gate arrays (FPGAs) to achieve over a trillion flips per second. Unlike standard bits or quantum qubits, p-bits flip between 0 and 1 with tunable probability, enabling the solution of stochastic problems like optimization. A key breakthrough was discovering a predictable design rule for inter-chip data exchange, allowing the FPGAs to behave as one machine without global lockstep synchronization. This innovation addresses previous scaling challenges, where earlier probabilistic computers with 8 p-bits (2019) and 7,200 p-bits (2023) were confined to single chips. The findings suggest a path toward building arbitrarily large, general-purpose probabilistic computers from diverse hardware.

Key takeaway

For AI Hardware Engineers evaluating next-generation computing architectures, this breakthrough in probabilistic computing offers a viable path for scaling beyond single-chip designs. You should consider the predictable design rule for inter-chip data exchange when developing multi-chip systems for stochastic problem-solving. This approach could enable general-purpose probabilistic machines, potentially reducing reliance on complex quantum hardware for certain optimization tasks.

Key insights

A new design rule enables scalable probabilistic computers with 1 million p-bits across multiple chips, overcoming synchronization hurdles.

Principles

• Probabilistic computers solve stochastic problems.
• P-bits bridge classical bits and quantum qubits.
• Inter-chip communication can scale without global lockstep.

Method

The new computer uses 18 networked FPGAs, implementing p-bits via software, and scales by applying a predictable design rule for inter-chip data exchange.

In practice

• Explore specialized chips like magnetic tunnel junctions.
• Combine CMOS with dense stochastic memory (MRAM).
• Apply design rule for multi-chip probabilistic systems.

Topics

• Probabilistic Computing
• P-bits
• FPGA
• Stochastic Problems
• Optimization Algorithms
• Scalable Computing

Best for: AI Scientist, AI Hardware Engineer, Research Scientist

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Editorial summary, takeaway, and curation by AIssential. Original article published by IEEE Spectrum.