Quantization Effects of Artificial Neural Networks for Embedded Edge-Computing Applications

2026-05-22 · Source: cs.NE updates on arXiv.org · Field: Technology & Digital — Artificial Intelligence & Machine Learning, Robotics & Autonomous Systems, Emerging Technologies & Innovation · Depth: Expert, medium

Summary

This study introduces a method for real-time waveform classification on FPGAs, specifically for self-triggered readout of SiPM sum signals in particle detectors. The approach utilizes look-up-table (LUT)-based 2-bit binary neural networks (BNNs) to achieve online data compression and reduce transmitted data volume. Traditional ADC data acquisition, often at 12-bit and 800 MSamples/s with a 100-sample window, requires processing within 125 ns to avoid dead time. The proposed BNNs, implemented with combinatorial LUTs, achieve sub 50 ns inference latencies. These BNNs feature 2-bit neuron values and 2-bit weights, with first-layer weight operations constrained to 4 options for 12-bit integer inputs, avoiding slow normalization. Training is performed using a genetic algorithm (GA) with O(1000) individuals per population, optimizing for fitness and minimizing non-zero weights. The method supports classifying SiPM signals into "good," "ugly," and "bad" categories, demonstrating robust classification for random inputs. While training takes considerable time compared to baseline CNNs (e.g., 128-4-6-8-2 with int8), the resulting hardware inference latency is suitable for real-time processing.

Key takeaway

For AI Hardware Engineers designing real-time edge processing systems, consider implementing 2-bit binary neural networks on FPGAs using combinatorial look-up tables. This approach, trainable via genetic algorithms, delivers sub-50ns inference latencies, crucial for applications like high-rate particle detector data compression. You should explore hardware-constrained learning to bypass traditional floating-point quantization bottlenecks and achieve dead-time-free online processing.

Key insights

LUT-based 2-bit BNNs trained with GAs enable sub-50ns real-time waveform classification on FPGAs.

Principles

• Combinatorial LUTs enable ultra-low latency inference.
• Hardware-constrained learning avoids slow floating-point conversions.
• Genetic algorithms can train non-differentiable binary networks.

Method

Design BNNs with 2-bit neurons/weights and LUT-based operations, then train using a genetic algorithm with elitism, optimizing for accuracy and weight sparsity.

In practice

• Implement BNNs on FPGAs for high-rate, low-latency edge processing.
• Use genetic algorithms for training non-differentiable hardware-aware NNs.
• Classify SiPM signals online to reduce data volume.

Topics

• FPGA
• Binary Neural Networks
• Genetic Algorithms
• Edge Computing
• Real-time Processing
• SiPM Signals

Best for: AI Scientist, AI Hardware Engineer, Machine Learning Engineer, Research Scientist

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Editorial summary, takeaway, and curation by AIssential. Original article published by cs.NE updates on arXiv.org.