ProWAFT: A ROMA-LPD Instance for Workload-Aware and Dynamic Fault Tolerance in FPGA-Based CNN Accelerators
Summary
ProWAFT is a proactive workload-aware fault-tolerance framework designed for FPGA-based Convolutional Neural Network (CNN) accelerators, addressing reliability concerns from transient faults in SRAM-based FPGAs at the network edge. Unlike always-on redundancy or reactive recovery, ProWAFT employs partial reconfiguration to selectively apply Triple Modular Redundancy (TMR) across reconfigurable partitions. The system quantifies workload criticality, models fault propagation, and accounts for reconfiguration overhead to minimize a composite objective across latency, energy, and reliability risk. Implemented on a Xilinx Zynq UltraScale+ ZCU104 platform with six reconfigurable regions, ProWAFT was evaluated using a 500-task trace derived from ResNet-18, MobileNetV2, and EfficientNet-Lite under time-varying Single Event Upset (SEU) injection. It demonstrated lower composite cost compared to static TMR and reactive reconfiguration, maintaining a high task success rate and near-baseline throughput with low online decision overhead.
Key takeaway
For Machine Learning Engineers deploying CNNs on edge FPGAs, ProWAFT offers a compelling alternative to static redundancy. You should consider implementing proactive, workload-aware fault tolerance using partial reconfiguration. This achieves high reliability without the substantial performance and energy overheads of always-on TMR. This approach maintains near-baseline throughput while significantly reducing composite cost, making it ideal for latency- and energy-constrained applications.
Key insights
ProWAFT dynamically applies TMR via partial reconfiguration to optimize fault tolerance in FPGA-based CNNs.
Principles
- Workload criticality informs dynamic fault tolerance.
- Partial reconfiguration enables selective redundancy.
- Optimize composite cost of reliability, latency, energy.
Method
ProWAFT quantifies workload criticality, models fault propagation and reconfiguration overhead, then selects TMR configurations via partial reconfiguration to minimize a composite objective of latency, energy, and reliability risk.
In practice
- Implement dynamic TMR on Zynq UltraScale+ FPGAs.
- Evaluate fault tolerance with ResNet-18, MobileNetV2.
- Achieve near-baseline throughput with proactive TMR.
Topics
- FPGA Accelerators
- CNN Inference
- Fault Tolerance
- Partial Reconfiguration
- Triple Modular Redundancy
- Edge AI
Best for: Computer Vision Engineer, Research Scientist, AI Hardware Engineer, Machine Learning Engineer, AI Scientist
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Editorial summary, takeaway, and curation by AIssential. Original article published by Computation and Language.