Registers Matter for Pixel-Space Diffusion Transformers

· Source: cs.CV updates on arXiv.org · Field: Technology & Digital — Artificial Intelligence & Machine Learning, Computer Vision · Depth: Expert, extended

Summary

A study on Diffusion Transformers (DiTs) reveals that while they do not exhibit the high-norm patch-token outliers common in Vision Transformers (ViTs), register tokens significantly enhance the convergence and generation quality of pixel-space DiTs. Unlike ViTs where registers absorb existing outliers, in DiTs, registers themselves develop high-norm tokens. This mechanism leads to cleaner, smoother intermediate feature maps, particularly at high noise levels, and reduces patch-token feature norms. Register tokens also specialize, acting as both norm sinks and encoders of global semantic information. The research notes that existing pixel-space DiT architectures, such as JiT, implicitly incorporate register-like behaviors through in-context conditioning. Motivated by these findings, a parameter-efficient dual-stream architecture is proposed, which processes register and patch tokens distinctly, improving generation quality on ImageNet 256x256 (e.g., FID from 3.71 to 3.48) with only a ~14% increase in model size and no runtime overhead.

Key takeaway

For Machine Learning Engineers optimizing pixel-space Diffusion Transformers, integrating register tokens is crucial for enhancing generation quality and convergence. Your models will benefit from cleaner internal representations and reduced patch-token feature norms. Consider implementing a parameter-efficient dual-stream architecture, specializing RMSNorm, adaLN, and MLP for register tokens, and introducing registers in deeper layers (e.g., 4-11) to achieve significant performance gains with minimal overhead. This approach can improve FID scores, as demonstrated by the 3.71 to 3.48 improvement.

Key insights

Register tokens, despite DiTs lacking ViT-like outliers, significantly improve pixel-space Diffusion Transformer performance by regularizing internal representations.

Principles

Method

A parameter-efficient dual-stream architecture processes register and patch tokens distinctly, sharing attention but specializing RMSNorm, adaLN, and MLP layers. Registers are introduced in deeper blocks (e.g., layers 4-11) for optimal effect.

In practice

Topics

Code references

Best for: Research Scientist, AI Scientist, Machine Learning Engineer, Computer Vision Engineer

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Editorial summary, takeaway, and curation by AIssential. Original article published by cs.CV updates on arXiv.org.