EdgeCortix Looks To Chiplets For Third-Gen Reconfigurable AI Chip

2026-03-27 · Source: Big Data & AI News - EE Times · Field: Technology & Digital — Artificial Intelligence & Machine Learning, Robotics & Autonomous Systems, Software Development & Engineering · Depth: Advanced, extended

Summary

EdgeCortix CEO Sakya Dasgupta discusses the company's reconfigurable dataflow architecture and its second-generation Sakura-II AI inference chip, which launched in 2024. The Sakura-II features a Dynamic Neural Accelerator (DNA) NPU, offering 60 TOPS at INT8, and is designed for energy efficiency, low latency, and high performance per dollar and per watt. The architecture minimizes external memory communication and allows dynamic runtime control of compute elements for optimized utilization and mixed precision (BF16, INT8, 4-bit approximation). EdgeCortix emphasizes a "software-first" approach with its Mera compiler, which supports heterogeneous hardware environments (ARM, x86, RISC-V) and integrates with platforms like HuggingFace. The company's chips are being deployed in diverse applications, including industrial automation, robotics, and notably, space applications with NASA, where Sakura-II demonstrated 10x higher radiation tolerance than some non-COTS products. EdgeCortix is also developing its third-generation Sakura-X chiplet platform, which will feature enhanced programmability and support for FP4.

Key takeaway

For AI Architects and Hardware Engineers evaluating edge AI solutions, EdgeCortix's Sakura-II and upcoming Sakura-X chiplet platform offer a compelling option for applications demanding low power, low latency, and high efficiency. Your designs can benefit from its radiation-tolerant capabilities for robust deployments in harsh environments like space, and its software-first compiler approach simplifies integration across diverse hardware. Consider its mixed-precision support and runtime reconfigurability for optimizing performance and power consumption for specific workloads.

Key insights

EdgeCortix's reconfigurable dataflow architecture and software-first approach optimize AI inference for power, latency, and cost efficiency.

Principles

• Minimize off-chip memory communication.
• Prioritize software-hardware co-design.
• Design for runtime reconfigurability.

Method

EdgeCortix's DNA architecture uses a dynamically controlled compute bus to optimize utilization and mixed precision, while the Mera compiler handles heterogeneous hardware and multi-platform model compilation.

In practice

• Utilize dynamic compute element control for power/performance trade-offs.
• Employ mixed precision (BF16, INT8, 4-bit) for accuracy/speed balance.
• Leverage compiler for multi-platform hardware integration.

Topics

• EdgeCortix
• Reconfigurable AI Chips
• Dynamic Neural Accelerator
• Mera Compiler
• Chiplet Architecture

Best for: AI Hardware Engineer, AI Architect, Director of AI/ML

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Editorial summary, takeaway, and curation by AIssential. Original article published by Big Data & AI News - EE Times.