Scalable On-Hardware Training of Quantum Neural Networks and Application to Clinical Data Imputation

· Source: Artificial Intelligence · Field: Technology & Digital — Artificial Intelligence & Machine Learning, Emerging Technologies & Innovation, Health & Medical Research · Depth: Expert, quick

Summary

A new training framework addresses the scalability bottleneck of Quantum Neural Network (QNN) training on quantum hardware, which traditionally faces gradient estimation costs growing quadratically with parameters. This framework reduces the cost to O(log n) in the number of qubits, making hardware-based optimization feasible for larger systems. It integrates a structured, subspace-preserving Butterfly circuit architecture with O(n log n) parameters and logarithmic depth, a layer-wise training strategy, and a parallelized parameter-shift rule that extracts all gradients in a constant number of circuit executions per layer. Validated on clinical data imputation using the MIMIC-III dataset, the framework enabled hybrid classical-quantum models to be trained directly on IonQ Forte Enterprise trapped-ion hardware at 16 qubits. These models matched or exceeded strong classical neural baselines in patient survival prediction and exhibited reduced variance.

Key takeaway

For AI Scientists and Machine Learning Engineers exploring Quantum Neural Networks for real-world applications, this framework offers a critical advancement. You should consider adopting this co-designed approach, which drastically reduces gradient estimation costs on hardware from O(n^2) to O(log n). This enables practical, scalable QNN training on near-term hardware, as demonstrated by its competitive performance in clinical data imputation and improved patient survival prediction.

Key insights

A novel QNN training framework reduces hardware gradient estimation costs from O(n^2) to O(log n), enabling scalable quantum computing applications.

Principles

Method

The method combines a Butterfly circuit architecture, a layer-wise training strategy, and a parallelized parameter-shift rule. This reduces distinct circuit evaluations per optimization step from O(n^2) to O(log n).

In practice

Topics

Best for: Research Scientist, AI Scientist, Machine Learning Engineer, AI Hardware Engineer

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Editorial summary, takeaway, and curation by AIssential. Original article published by Artificial Intelligence.