Attention Decode on AMD MI450 GPUs: A Gluon Kernel Optimization Guide
Summary
AMD's blog details optimizing attention decode kernels for its MI450 series GPUs using Gluon, a Triton-based DSL. The MI450 introduces hardware features like the Tensor Data Mover (TDM) for asynchronous memory transfers, increased Local Data Share (LDS) to 320 KB, and workgroup clusters. The optimization guide focuses on four key areas: optimizing tensor layouts for WMMA operations, enhancing data loading via TDM by reshaping K/V tensors for direct-to-LDS transfers, implementing multi-stage pipelines (up to four-stage with triple buffering) to overlap memory access and computation, and parallelizing with Split-k using workgroup clusters to improve GPU saturation. An optimized Gluon kernel achieved 17.10 TB/s (85% of 20 TB/s peak) for GQA and 16.65 TB/s (83%) for MQA, demonstrating significant performance gains for memory-bound LLM inference workloads with context lengths up to 65536.
Key takeaway
For Machine Learning Engineers optimizing LLM inference on AMD MI450 GPUs, you should prioritize kernel-level optimizations that exploit MI450's unique hardware. Focus on custom Gluon kernels to manage tensor layouts, utilize TDM for direct memory-to-LDS transfers, implement multi-stage pipelining with triple buffering, and employ workgroup clusters for Split-k parallelism. This approach can yield significant performance gains, reaching up to 85% of peak HBM bandwidth, crucial for scaling agentic AI applications with long context lengths.
Key insights
Optimizing LLM attention decode on AMD MI450 GPUs requires deep hardware-software co-design, utilizing TDM, pipelining, and Split-k for peak HBM bandwidth.
Principles
- Memory-bound workloads benefit from direct-to-LDS data paths.
- Overlap memory transfers and compute to hide latency.
- Explicit tensor layout control is crucial for WMMA performance.
Method
Design high-performance kernels by optimizing WMMA tensor layouts, using TDM for direct global-to-LDS data loading, implementing multi-stage pipelines for latency hiding, and parallelizing with Split-k via workgroup clusters.
In practice
- Reshape K/V tensors to ensure TDM innermost dimension is ≥256 bytes.
- Use triple buffering in pipelines for longer lookahead.
- Employ multi-CTA programming in Gluon for Split-k parallelism.
Topics
- AMD MI450 GPUs
- Attention Decode
- Gluon Kernel Optimization
- LLM Inference Performance
- HBM Bandwidth
- Split-k Parallelization
Code references
Best for: Machine Learning Engineer, AI Hardware Engineer
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Editorial summary, takeaway, and curation by AIssential. Original article published by AMD ROCm Blogs.