ITF World 2026: The Semiconductor Industry Enters a New Systems Era

2026-07-13 · Source: Big Data & AI News - EE Times · Field: Technology & Digital — Artificial Intelligence & Machine Learning, Emerging Technologies & Innovation, Semiconductor & Hardware Architecture · Depth: Advanced, short

Summary

At imec's ITF World 2026 conference, the semiconductor industry signaled a shift from traditional transistor scaling to a "new systems era" defined by complex integration. AI is exposing bottlenecks that require innovation beyond logic, focusing on memory bandwidth, interconnects, power, thermal management, packaging, and software. Imec CEO Patrick Vandenameele emphasized deep co-optimization across the entire computing stack. Key themes explored include Europe's strategy in a chiplet-driven world, heterogeneous large-scale integration as a successor to SoC, and CMOS 2.0 pushing scaling via advanced 3D integration. Researchers also detailed the evolution of optics closer to the processor, from co-packaged to 2.5D and 3D optical I/O, to efficiently move AI data. Furthermore, advanced semiconductor manufacturing is transforming quantum computing experiments into scalable systems. This collective progress underscores that future advancements will stem from integrating compute, memory, photonics, packaging, power, and quantum technologies into coherent, scalable systems.

Key takeaway

For Directors of AI/ML evaluating future system designs, recognize that traditional transistor scaling is insufficient. Your strategy must prioritize heterogeneous integration and full-stack co-optimization, moving beyond monolithic SoCs. Focus on integrating chiplets, advanced 3D packaging, and evolving optical I/O solutions (2.5D/3D) to address AI's memory and interconnect bottlenecks. This shift demands closer collaboration across design, manufacturing, and software teams to build economically and efficiently scalable systems.

Key insights

The semiconductor industry is shifting to a systems-level integration approach, driven by AI's demands for full-stack co-optimization.

Principles

• Deep co-optimization across the computing stack is essential.
• Heterogeneous integration succeeds traditional SoC designs.
• Scaling now involves circuit repartitioning, not just transistor shrinks.

Method

Achieve future progress through deep co-optimization across the computing stack, involving AI architects, chip designers, equipment suppliers, and system developers in closer collaboration.

In practice

• Evolve optics from co-packaged to 2.5D and 3D optical I/O.
• Utilize chiplets for modular, heterogeneous system design.
• Apply advanced lithography to scale quantum systems.

Topics

• Semiconductor Industry
• Heterogeneous Integration
• Chiplets
• Silicon Photonics
• Quantum Computing
• AI Hardware
• 3D Integration

Best for: AI Hardware Engineer, AI Architect, Director of AI/ML

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• Imec’s Patrick Vandenameele: Full-stack Innovation Is the Name of the Game — Future AI progress depends on deep, full-stack co-optimization across compute, memory, photonics, and packaging.
• What They Just Built Is Unreal — Imec drives future computing by inventing post-Moore's Law chip architectures and materials, enabling continued technological advancement.
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• Is Optical Scale-Up Finally Approaching? — The "copper wall" in AI scale-up networks is driving a shift towards co-packaged optical interconnects, now feasible due to manufacturing maturity.

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Editorial summary, takeaway, and curation by AIssential. Original article published by Big Data & AI News - EE Times.