Google unveils two new TPUs designed for the "agentic era"

· Source: AI - Ars Technica · Field: Technology & Digital — Artificial Intelligence & Machine Learning, Cloud Computing & IT Infrastructure · Depth: Intermediate, medium

Summary

Google has unveiled its eighth-generation Tensor Processing Units (TPUs), the TPU 8t for training and the TPU 8i for inference, designed for the "agentic era" of AI. The TPU 8t is engineered to accelerate frontier AI model training, reducing timelines from months to weeks, featuring pods with 9600 chips, two petabytes of shared high-bandwidth memory, and 121 FP4 EFlops of compute per pod, nearly triple the previous Ironwood generation. It boasts a "goodpute" rate of 97% for efficient computation. The TPU 8i, optimized for inference, runs in larger pods of 1,152 chips, offers 11.6 EFlops per pod, and triples on-chip SRAM to 384 MB for longer context windows. Both new TPUs utilize Google's custom Axion ARM CPU host and are designed for enhanced power and cooling efficiency, claiming twice the performance per watt compared to Ironwood and six times more computing power per unit of electricity in co-designed data centers.

Key takeaway

For CTOs and VP of Engineering evaluating AI infrastructure, Google's new TPU 8t and 8i offer a specialized, efficient alternative to general-purpose accelerators. Your teams should consider these TPUs for accelerating both the training of large-scale frontier models and the efficient deployment of agentic AI systems, potentially reducing operational costs and development timelines, especially if you are already invested in the Google Cloud ecosystem.

Key insights

Google's new dual-chip TPU architecture optimizes AI training and inference for the emerging "agentic era."

Principles

Method

Google's approach involves developing distinct TPU architectures (8t for training, 8i for inference) and integrating them with custom ARM CPUs and co-designed data centers for end-to-end efficiency.

In practice

Topics

Best for: CTO, VP of Engineering/Data, MLOps Engineer, AI Hardware Engineer, AI Architect, Director of AI/ML

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Editorial summary, takeaway, and curation by AIssential. Original article published by AI - Ars Technica.