Rethinking the Logic-Routing Tradeoff in FPGAs

· Source: Big Data & AI News - EE Times · Field: Technology & Digital — Artificial Intelligence & Machine Learning, Robotics & Autonomous Systems, Emerging Technologies & Innovation · Depth: Intermediate, short

Summary

Efinix has launched its Titanium Edge family of FPGAs, targeting edge AI applications with soft or hard RISC-V cores featuring AI instruction extensions. This new family leverages Efinix's proprietary XLR (exchangeable logic and routing) logic cell, which dynamically allocates silicon space for either logic or routing. This innovation addresses the traditional FPGA tradeoff, enabling similar or greater performance compared to top-performing FPGAs, but at half the power and half the die area. The Titanium Edge FPGAs also offer reduced static power consumption, single-event upset (SEU) protection, post-quantum security, and enhanced high-speed I/O, supporting up to 2.5 Gb/s MIPI interfaces with up to eight lanes for applications like robotics. Some parts will be co-packaged with Winbond HyperRAM, a DRAM die behaving like SRAM, to store intermediate AI inference weights or video frames, further reducing area and simplifying memory sourcing. Some Titanium Edge parts are already shipping, with the full family expected by the end of 2026.

Key takeaway

For Robotics Engineers designing edge AI systems, Efinix's Titanium Edge FPGAs offer a compelling alternative to fixed-function SoCs. You can achieve similar or better performance at half the power and die area by leveraging their dynamic logic/routing cells. Consider these FPGAs for integrating custom sensors or performing front-end processing, especially with their high-speed MIPI support and co-packaged HyperRAM options, which simplify memory sourcing and reduce board space.

Key insights

Efinix's XLR logic cell dynamically reconfigures silicon for logic or routing, achieving superior FPGA performance, power, and area efficiency.

Principles

Method

Efinix's software determines and allocates the required logic and routing dynamically within its XLR logic cells across different areas of an FPGA design.

In practice

Topics

Best for: Machine Learning Engineer, Computer Vision Engineer, AI Hardware Engineer, AI Engineer, Robotics Engineer

Related on AIssential

Open in AIssential →

Editorial summary, takeaway, and curation by AIssential. Original article published by Big Data & AI News - EE Times.