HighTide: An Agent-Curated Open-Source VLSI Benchmark Suite
Summary
HighTide is a new, AI-assisted open-source VLSI benchmark suite designed to address the limitations of existing static benchmarks. It offers a diverse collection of designs spanning multiple hardware description languages (Verilog, SystemVerilog, Chisel, Python-based generators) and three technology platforms: ASAP7 (7 nm), NanGate45 (45 nm), and SkyWater 130nm (130 nm). The suite features Bazel-based incremental RTL-to-GDS compilation with remote caching and incorporates twelve Claude Code agent skills for design curation, flow optimization, tool reference, and meta-maintenance. These agents utilize per-design decision logs as long-term memory, ensuring tuning rationale propagates across the suite. HighTide significantly reduces the RISC-V CPU share from approximately 59% in older suites to 30%, allocating more to ML accelerators, NoCs, and GPGPUs, with cell counts ranging from under 20k to over 1.5M. Its infrastructure includes RTL compilation verification for stable releases, ensuring it evolves with the open-source hardware ecosystem.
Key takeaway
For ML engineers and EDA researchers developing or benchmarking VLSI tools, HighTide offers a critical, continuously updated dataset. You should integrate HighTide into your evaluation workflows to train models on diverse, contemporary designs, avoiding overfitting on stale data. Its AI-assisted curation and broad coverage across HDLs and technology nodes (7 nm, 45 nm, 130 nm) ensure more generalizable results. This approach will lead to more reproducible outcomes for your next-generation hardware designs.
Key insights
HighTide uses AI agents and a dynamic infrastructure to maintain a diverse, evolving VLSI benchmark suite.
Principles
- Benchmarks must evolve with hardware.
- AI agents can automate design curation.
- Cross-design memory improves tuning.
Method
HighTide employs Claude Code agents with twelve skills for design discovery, integration, cross-platform porting, upstream tracking, debugging, PPA optimization, and meta-maintenance, backed by per-design decision logs.
In practice
- Use Git submodules for versioned snapshots.
- Implement remote caching for build artifacts.
- Track upstream tool bugs with workarounds.
Topics
- VLSI Benchmarking
- AI Agents
- Open-Source Hardware
- RTL-to-GDS Flow
- EDA Tools
- SoC Design
Code references
- VLSIDA/HighTide
- ABKGroup/FakeRAM2.0
- chipsalliance/rocket-chip
- bespoke-silicon-group/bsg_fakeram
- antonblanchard/microwatt
Best for: AI Scientist, Research Scientist, Machine Learning Engineer, AI Engineer
Related on AIssential
Editorial summary, takeaway, and curation by AIssential. Original article published by cs.SE updates on arXiv.org.