Maximizing Parallel Execution of Series-Parallel Task Graphs for Safety-Critical Embedded Control

2026-07-01 · Source: cs.SE updates on arXiv.org · Field: Technology & Digital — Robotics & Autonomous Systems, Software Development & Engineering, Artificial Intelligence & Machine Learning · Depth: Advanced, extended

Summary

The paper introduces a Maximum Parallel Execution (MPE) problem for series-parallel task graphs, aiming to accelerate safety-critical embedded control programs on FPGAs. It formulates MPE as a weighted clique-partitioning problem under a staged batching model, where compatible tasks within a batch execute in parallel, and batches are launched sequentially. To solve this, the authors propose a Lagrangian-based Iterative Heuristic (LIH). Experiments show LIH matches the exact optimum in 91.25% of comparable instances with an average gap of 0.073% and an average runtime of 18.19 ms, significantly outperforming an exact branch-and-bound baseline that averages 22.83 seconds. For larger instances (50-100 nodes), LIH consistently yields 9.70% to 15.91% smaller makespans than a randomized greedy approach. A PLC ladder-logic case study demonstrates LIH's ability to convert programs into FPGA-oriented HDL, achieving a 1.642x cycle speedup and 58.10% staged-makespan reduction.

Key takeaway

For AI Hardware Engineers or Robotics Engineers designing safety-critical embedded control systems, consider adopting the Lagrangian-based Iterative Heuristic (LIH) for task graph optimization. This method efficiently identifies parallel execution stages, significantly reducing control cycle latency and improving system responsiveness on FPGAs. You should integrate LIH into your design flow to automatically convert sequential control logic into highly parallel, deterministic hardware implementations, especially for complex systems with many interdependent tasks.

Key insights

A Lagrangian-based heuristic efficiently optimizes parallel execution for safety-critical embedded control on FPGAs by batching compatible tasks.

Principles

• Series-parallel task graphs model dependencies in embedded control.
• Maximizing parallel execution minimizes makespan in FPGA-oriented systems.
• Lagrangian pricing guides selection of valuable parallel execution batches.

Method

The Lagrangian-based Iterative Heuristic (LIH) constructs a pricing-filtered pool of candidate batches, uses Lagrangian pricing to guide column selection, and employs a repair procedure to recover a legal, acyclic clique partition.

In practice

• Convert PLC ladder logic programs into MPE graphs for optimization.
• Generate FPGA-oriented HDL from optimized batching plans.
• Achieve significant cycle speedup and makespan reduction in embedded control.

Topics

• Embedded Control
• FPGA Acceleration
• Series-Parallel Graphs
• Task Scheduling
• Lagrangian Relaxation
• Clique Partitioning
• PLC Ladder Logic

Code references

• UniboSecurityResearch/PLC-LD-dataset

Best for: Research Scientist, AI Scientist, Robotics Engineer, AI Hardware Engineer

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Editorial summary, takeaway, and curation by AIssential. Original article published by cs.SE updates on arXiv.org.