Space Industry Is Standardizing on RISC-V

2026-06-18 · Source: Big Data & AI News - EE Times · Field: Technology & Digital — Robotics & Autonomous Systems, Artificial Intelligence & Machine Learning, Emerging Technologies & Innovation · Depth: Advanced, medium

Summary

The space industry is rapidly standardizing on the open-standard RISC-V instruction set architecture, moving away from legacy SPARC and PowerPC systems. This shift was a key discussion point at the RISC-V Summit Europe 2026, involving experts from the European Space Agency, NASA's Jet Propulsion Laboratory, Microchip, and Frontgrade Gaisler. The transition is driven by the high cost of updating 32-bit legacy systems to 64-bit, the need to reduce technical debt, and the demand for processors tailored to tight size, weight, and power limits for emerging applications like neural networks. Frontgrade Gaisler, a European Space Agency spinoff, is introducing its NOEL line, including the GR765, an eight-core radiation-hardened processor supporting both SPARC and RISC-V. In the U.S., Microchip is developing the PIC64-HPSC for NASA, featuring eight SiFive RISC-V cores, Ethernet, and PCI Express for next-generation missions requiring enhanced on-board processing and cybersecurity. Commercial space, including SpaceX and Europe's IRIS² project, is also adopting RISC-V for orbital data centers and future 6G networks.

Key takeaway

For AI Hardware Engineers designing next-generation space systems, the industry's standardization on RISC-V means you should prioritize this architecture. Your designs must incorporate 64-bit capabilities and radiation hardening. This supports advanced on-board processing and neural networks. Consider hybrid solutions for backward compatibility during transitions. This shift enables reduced technical debt and supports future space-based hypercomputing and 6G networks.

Key insights

The space industry is rapidly adopting RISC-V as its standard processor architecture due to its open nature, cost benefits, and adaptability for advanced missions.

Principles

• Open standards reduce technical debt.
• Backward compatibility eases transitions.
• Space computing demands radiation-hardened, adaptable designs.

Method

Frontgrade Gaisler developed the NOEL processor line, including the GR765, which integrates both SPARC and RISC-V pipelines, allowing boot-time selection and backward compatibility with legacy code to facilitate architectural migration.

In practice

• Develop 64-bit processors for space.
• Integrate neural networks on-board.
• Build orbital data centers.

Topics

• RISC-V
• Space Computing
• Radiation Hardened Processors
• SPARC Architecture
• On-board Processing
• 6G Networks
• Hypercomputing Continuum

Best for: AI Hardware Engineer, AI Architect, Research Scientist

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Editorial summary, takeaway, and curation by AIssential. Original article published by Big Data & AI News - EE Times.