Exclusive: Allen Wu on Disrupting $100M Cost of Building Custom AI Chips

2026-03-05 · Source: Big Data & AI News - EE Times · Field: Technology & Digital — Artificial Intelligence & Machine Learning, Robotics & Autonomous Systems, AI Hardware Design · Depth: Intermediate, long

Summary

CoreLab Technology, founded by former Arm China president Allen Wu, aims to reduce the entry-level cost of custom AI chip development by 75% or more from the traditional $100 million. The company leverages RISC-V as a baseline to enable heterogeneous custom AI chips, integrating various processor architectures like CPUs, GPUs, and DSPs into a unified platform. CoreLab's approach focuses on creating an "Android platform for compute" that simplifies the integration of diverse IP blocks and shared software pipelines, addressing the evolving needs of physical AI compute, particularly in robotics. Their first concrete output is the Atlantis platform, featuring eight Tenstorrent high-performance cores, CoreLab's RISC-V real-time security, and power management IP, with development boards expected in Q4 2026.

Key takeaway

For CTOs and engineering teams developing custom AI hardware, CoreLab Technology's approach offers a compelling alternative to the high costs and complexities of traditional chip design. By embracing an open, heterogeneous RISC-V-based platform, you can significantly reduce development costs and accelerate time-to-market for specialized AI compute solutions, particularly for rapidly evolving fields like robotics. Consider exploring modular platforms like Atlantis to experiment with custom architectures before committing to full SoC development.

Key insights

Heterogeneous custom AI chip development can be made affordable and accessible using an open, modular RISC-V baseline.

Principles

• Future AI processors will be custom fusion processors (XPUs).
• Open architectures enable mixing and matching diverse processor IP.
• Standardized platforms reduce complexity for custom hardware development.

Method

CoreLab Technology builds an open architecture ASIC platform using RISC-V as a common baseline, allowing CPUs, GPU-type cores, and domain-specific accelerators to share the same underlying software pipeline for lower cost and easier integration.

In practice

• Utilize RISC-V for custom AI chip development.
• Integrate diverse processor architectures on a single platform.
• Explore platforms like Atlantis for early-stage experimentation.

Topics

• AI Chip Design
• RISC-V Architecture
• Heterogeneous Computing
• Robotics AI
• Custom Processors

Best for: Investor, Entrepreneur, CTO, AI Hardware Engineer, AI Architect, Robotics Engineer

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Editorial summary, takeaway, and curation by AIssential. Original article published by Big Data & AI News - EE Times.