The PQC Silicon Is Here Today for Tomorrow’s Quantum Threats

2026-06-26 · Source: Big Data & AI News - EE Times · Field: Technology & Digital — Cybersecurity & Data Privacy, Emerging Technologies & Innovation · Depth: Intermediate, short

Summary

New security chips featuring hardware accelerators for post-quantum cryptography (PQC) are emerging to future-proof connected devices against quantum threats. STMicroelectronics' ST54M chip, released on 06.26.2026, integrates a PQC hardware accelerator with an NFC controller, embedded secure element (eSE), and eSIM, supporting major PQC algorithms like ML-KEM and ML-DSA for secure mobile use cases. Similarly, Samsung's S3SSE2A chip, displayed at CES 2026, combines PQC with an eSE, implementing FIPS 204 operations and achieving approximately 17x faster PQC computation than software-only solutions. Other vendors like Infineon and Microchip are also incorporating PQC into their MCUs and MPUs, with products like Infineon's PSOC Control C3 and Microchip's PIC64HX family supporting NIST FIPS 203 and FIPS 204 algorithms. The urgency stems from the "harvest now, decrypt later" threat, with quantum computers potentially compromising current encryption by 2028, reinforced by the U.S. Government's Executive Order 14409. Keysight Technologies is also offering PQC algorithm testing platforms.

Key takeaway

For device manufacturers developing connected products, you must prioritize integrating PQC-enabled silicon now to mitigate the "harvest now, decrypt later" quantum threat. Your current encryption could be compromised by 2028, making early adoption of solutions like STMicroelectronics' ST54M or Samsung's S3SSE2A critical for long-term security. Begin evaluating PQC hardware accelerators and secure elements to ensure your next-generation devices comply with emerging standards like NIST FIPS 203/204 and CNSA Suite 2.0.

Key insights

Hardware-accelerated PQC silicon is available now to counter imminent quantum decryption threats.

Principles

• Dedicated PQC hardware offers superior performance and security.
• Hybrid cryptographic approaches facilitate PQC transition.
• Independent security processing enhances device protection.

Method

Integrating PQC hardware accelerators into secure elements and NFC controllers enables robust, future-proof device security against quantum threats.

In practice

• Implement PQC algorithms like ML-KEM and ML-DSA.
• Utilize secure elements for key storage and processing.
• Test PQC implementations against side-channel attacks.

Topics

• Post-Quantum Cryptography
• Hardware Security Modules
• Quantum Threats
• Secure Elements
• NIST PQC Standards
• Side-Channel Attacks

Best for: CTO, VP of Engineering/Data, AI Hardware Engineer, AI Security Engineer, Security Engineer

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Editorial summary, takeaway, and curation by AIssential. Original article published by Big Data & AI News - EE Times.