BitFair: A 12nm Bit-Serial CNN Accelerator with Learnable Early Termination and Adaptive Bit Ordering for Ultra-Low-Power XR Vision

2025-03-15 · Source: cs.CV updates on arXiv.org · Field: Technology & Digital — Artificial Intelligence & Machine Learning, Robotics & Autonomous Systems, Emerging Technologies & Innovation · Depth: Expert, extended

Summary

BitFair is a 12nm FinFET bit-serial CNN accelerator designed for ultra-low-power Extended Reality (XR) vision applications, addressing strict power and latency requirements. It features learnable bit-level early termination and adaptive bit ordering, which dynamically exploit sparsity to reduce computation. Implemented with a 0.34 mm2 core area and 104 KB on-chip memory, BitFair operates from 0.55 to 0.70 V, achieving sub-millisecond latency (0.12-1.55 ms) and up to 117.0 BTOPS/W. On IBM DVS128 Gesture and N-MNIST datasets, it reaches 96.5% and 97.7% accuracy, respectively, demonstrating 4.0-22.1x effective energy efficiency improvements and up to 9.2% higher accuracy over prior fabricated XR vision accelerators.

Key takeaway

For AI Hardware Engineers designing accelerators for XR wearables, BitFair demonstrates a compelling approach to meet stringent power and latency budgets. You should consider integrating learnable early termination and adaptive bit ordering into your bit-serial CNN designs. This can yield significant energy efficiency gains and sub-millisecond latency, crucial for immersive user experiences, without sacrificing accuracy.

Key insights

BitFair optimizes bit-serial CNNs for XR via learnable early termination and adaptive bit ordering.

Principles

• Dynamic bit-level sparsity can be exploited for energy efficiency.
• Layer-specific bit ordering maximizes early termination opportunities.
• Gradient-based optimization can tune hardware-aware thresholds.

Method

BitFair uses gradient-based training for layer-wise early termination thresholds and a greedy search algorithm for adaptive bit ordering, optimizing for efficiency and accuracy.

In practice

• Apply learnable thresholds to CNNs for dynamic sparsity exploitation.
• Implement adaptive bit ordering for bit-serial accelerators.
• Target event-driven vision tasks for high efficiency gains.

Topics

• CNN Accelerator
• Bit-Serial Computing
• Early Termination
• Adaptive Bit Ordering
• Extended Reality
• Ultra-Low-Power

Best for: Research Scientist, AI Hardware Engineer, AI Scientist, Computer Vision Engineer

Related on AIssential

• Energy-Efficient CNN Acceleration with MSDF Digit-Serial Arithmetic on FPGA — Merging multiply-add operations in digit-serial arithmetic significantly reduces latency and boosts energy efficiency for CNN acceleration on FPGAs.
• Scalable, Energy-Efficient Optical-Neural Architecture for Multiplexed Deepfake Video Detection — A hybrid optical-neural architecture significantly enhances deepfake detection throughput, energy efficiency, and robustness.
• NeuronFabric: A Software Reference Architecture for On-Chip Transformer Training with Local Adam — NeuronFabric enables memory-efficient on-chip transformer training using local Adam updates and a BF16W mixed-precision approach.
• An affordable hardware-aware neural architecture search for deploying convolutional neural networks on ultra-low-power computing platforms — A lightweight hardware-aware NAS generates tiny, accurate CNNs for ultra-low-power microcontrollers, enabling efficient embedded AI.
• A Hardware-Aware, Per-Layer Methodology for Post-Training Quantization of Large Language Models — SOP quantization achieves near-lossless LLM fidelity at 4.5-6 bpw using hardware-aware, per-layer codebook optimization.
• The Benchmark Behind the Next Wave of Ultra-Low-Power AI — MLPerf Tiny standardizes ultra-low-power AI benchmarking by measuring energy, latency, and accuracy across diverse hardware.

Open in AIssential →

Editorial summary, takeaway, and curation by AIssential. Original article published by cs.CV updates on arXiv.org.