OSTEP Chapter 13: The Abstraction of Address Spaces

2026-03-26 · Source: Metadata · Field: Technology & Digital — Software Development & Engineering, Artificial Intelligence & Machine Learning · Depth: Novice, short

Summary

Chapter 13 of OSTEP details how modern operating systems abstract physical hardware, focusing on the evolution and components of address spaces. Early computing lacked memory abstraction, with TinyOS sensor nodes in 2002 operating on 64KB of memory, compiling OS and application as a single process with static memory allocation. The shift began with multiprogramming to increase CPU utilization, followed by time sharing, which initially involved slow disk-based context switching. To improve efficiency, OSes started keeping multiple processes resident in memory. The address space abstraction, a program's view of memory, comprises program code, a downward-growing heap, and an upward-growing stack. This virtualization aims for transparency, efficiency, and protection. These principles extend to modern hardware like GPUs, which handle thousands of threads, though the "memory wall" in AI accelerators, particularly for LLMs, necessitates solutions like High Bandwidth Memory (HBM), tiered memory, and cache offloading to manage terabytes of data and avoid exhausting limited GPU VRAM.

Key takeaway

For software engineers optimizing system performance, understanding address space abstraction is crucial. You should recognize how virtual memory provides process isolation and efficient resource sharing. When designing for modern AI workloads, consider the "memory wall" challenge. Implement strategies like tiered memory or cache offloading. This manages large LLM KV caches and maximizes GPU HBM utilization, ensuring your applications scale effectively.

Key insights

Operating systems abstract physical memory into virtual address spaces for transparency, efficiency, and protection.

Principles

• Multiprogramming increases CPU utilization.
• Address spaces ensure process isolation.
• Virtualization prioritizes transparency, efficiency, protection.

In practice

• Use HBM for high-bandwidth data.
• Implement tiered memory for LLMs.
• Employ cache offloading for KV caches.

Topics

• Operating Systems
• Virtual Memory
• Address Spaces
• Memory Management
• GPUs
• LLM Optimization
• Process Isolation

Best for: AI Student, Software Engineer, Machine Learning Engineer

Related on AIssential

• NVIDIA drops DGX Station for Windows (1-Trillion Parameter desktop). Who else is ready to run LLaMA-Behemoth locally? — Aggressive quantization remains crucial for local inference of trillion-parameter models, even with powerful new hardware.
• Flush With Cash From OpenAI, Opal Is Making an AI-Powered Audio Gadget — Opal, funded by OpenAI, is expanding from webcams into AI-powered audio hardware.
• Microsoft Build: MAI-Thinking-1 and MAI Family models, Surface RTX Spark Dev Box, and OpenClaw in Windows — Microsoft is integrating its AI stack from custom silicon to frontier models and agent-native OS, emphasizing transparency and clean data.
• Extreme Low-Bit Inference in Reasoning Models: Failure Modes and Targeted Recovery — Aggressive 2-bit quantization in LRMs causes specific generation pathologies, not just accuracy drops, which can be mitigated.
• Accelerate LLM model loading and increase context windows with GPUDirect on Amazon FSx for Lustre and TurboQuant — Direct storage-to-GPU data paths and KV cache compression drastically cut LLM load times and expand context windows.
• Unbox one of NVIDIA's first co-packaged optics switches with us. See why we bet on CPO early. — Co-packaged optics (CPO) significantly improves power efficiency and reliability in large-scale GPU cluster networking.

Open in AIssential →

Editorial summary, takeaway, and curation by AIssential. Original article published by Metadata.